Koreans created the first 3D NAND chip with 300 layers

The previous record holder for 3D NAND memories – a 238-layer SK Hynix chip
(photo: SK Hynix)

South Korean memory manufacturer SK Hynix announced that it has created the world’s first 3D NAND chip with more than 300 layers. This was announced by company representatives during the ISSCC 2023 conference.

The development is the work of 35 engineers, which once again emphasizes the complexity of the technological process for the production of multilayer flash memory. The team not only increased the recording density, but also significantly increased the throughput of the chips: from 164 MB/s to 194 MB/s.

SK Hynix engineers have worked in two main and most important areas: increasing recording density (reducing the cost of storing each bit of data) and increasing performance.

With the advent of “multi-story” 3D NAND, increasing density has become much easier in concept, but difficult to execute—requiring an increase in the number of layers while decreasing the pitch between layers. But this leads to an increase in the resistance of the wordline (WL) connecting the cells in the row of the matrix. This growth must be compensated for in one way or another, otherwise speed and energy efficiency will deteriorate.

SK Hynix’s prototype NAND memory chip with more than 300 layers consists of tri-bit cells (TLC, three-level cells) and has a capacity of 1 terabit (Tbit). Due to the increase in the number of layers, the cell density has increased from 11.55 Gb/mm2 (for 238-layer memory) to more than 20 Gb/mm2.

Overall memory performance is boosted in five separate ways, generally aimed at speeding up write, erase and read processes. To do this, the designers have changed the sequences and timing of the commands.

In particular, a triple check programming method (TPGM) has been implemented instead of the previous double check (DPGM). The new method divides the cells into four groups instead of three. TPGM technology reduces the tPROG parameter and cell programming time by about 10%.

Additionally, the tPROG parameter is also reduced by the new Adaptive Unselected Row Preload (AUSP) technology. This speeds up the cells by about 2%. Additional acceleration is also obtained by reducing the capacitive loading of the WL line, thanks to the programmable dummy row (PDS) method.

The All Pass Rise (APR) method, on the other hand, leads to a decrease in the read time (tR), which is expressed in a decrease in the response time of the WL line to a new voltage level and improves the read time by 2%. Finally, the PLRR (Plane Level Repeat Read) method is used to improve the quality of service during cell erasure.

All these improvements taken together make it possible to increase the speed of 1Tbit 3D NAND TLC from 164 MB/s to 194 MB/s while simultaneously increasing the write density. SK Hynix did not disclose a production timetable for the new NAND memory. It can be expected that such chips will appear no earlier than the beginning of next year.

Meanwhile, 3D NAND chips with over 230 layers will be produced this year, the technology for which has already been adopted to one degree or another by all the major players in the NAND market.

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